Silicon carbide substrate supply sets how many starting wafers exist. Device roadmaps set which MOSFET or diode designs want to ship. Between those two sentences sits epitaxy: the grown layer where thickness, doping, and killer defects either earn a wafer a lot assignment or send it back as expensive scrap.
Teams that only track boule diameter transitions discover too late that epi yield—not crystal count—was the real throttle on a power-module ramp.
What the map is for
An epi defect map is not wallpaper for a yield review. It is a disposition tool:
- Which zones stay inside thickness and doping windows.
- Which defect classes are killers for the target device (micropipes, triangles, stacking faults—named and counted, not “particles”).
- Which wafers may enter lithography versus which must be reworked or dropped.
Color without disposition rules is decoration.
Process habits that keep maps honest
Recipe freezes without metrology freezes are fiction. Gas-panel drift, susceptor age, and clean-down intervals move defect signatures before SPC charts look dramatic. Plants that treat epi maps as lot passports—linked to MES genealogy—contain excursions faster than plants that store PNGs on a shared drive.
A short rule set that holds:
- One golden map definition per device family; no ad-hoc color scales in meetings.
- Killer-defect taxonomy owned by process engineering, not by the slide author of the week.
- Hold lots when map coverage or tool correlation fails—not only when averages look red.
Substrate supply briefs own crystal and wafering capacity. SiC/GaN device briefs own switching loss and packaging. Package test owns outgoing screens. This page owns epitaxy as the gate that turns a wafer into a candidate die. Do not celebrate a substrate contract and ignore the epi map.