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Sector · Semiconductors · 25 May 2026

High-NA EUV becomes a fab CapEx and process decision

0.55-NA EUV tools are entering qualification for sub-2nm work—but cost, throughput, and whether multipatterning on 0.33-NA still wins remain the real roadmap questions.

High-NA EUV becomes a fab CapEx and process decision

Advanced logic is no longer only a packaging story. At the front end, High-NA EUV (0.55 numerical aperture) is moving from lab demonstrations into tool installs and process qualification for the ångström-class nodes that AI accelerators and premium SoCs will need.

ASML’s High-NA platform is a different machine class from today’s 0.33-NA EUV: larger optics, higher capital cost per tool, and a full rework of resist, etch, and metrology around finer resolution. Research institutes and leading foundries have been installing systems for development and early manufacturing readiness through 2025–2026.

What High-NA is meant to buy

  • Fewer multipatterning steps — Where one High-NA exposure can replace multi-pass 0.33-NA sequences, cycle time and defect opportunity can fall.
  • Design freedom — Finer features and denser patterns for GAA/nanosheet transistors and tighter interconnect.
  • Node competitiveness — Access to the patterning toolkit that defines who can run the most advanced AI silicon.

What still decides adoption

Each tool costs on the order of hundreds of millions of dollars. Throughput, overlay, stitching constraints, and cost per wafer pass must beat extended multipatterning on installed 0.33-NA fleets. Some foundry roadmaps still lean on low-NA EUV plus computational lithography where the economics win. High-NA is therefore a CapEx and process-cost decision—not an automatic swap.

Metrology and inspection intensity also rise. Finer features demand tighter process control, which feeds the equipment market around the scanner itself.

What to watch next

  1. Which nodes and which customers actually tape out with High-NA versus extended 0.33-NA flows.
  2. Wafer-per-hour and yield learning curves on EXE-class production tools.
  3. How High-NA capacity concentrates among a handful of leading-edge fabs—and what that means for AI chip supply geography.

Front-end lithography and back-end packaging are now dual bottlenecks. High-NA is the front-end chapter of the same industrial story: who can print, package, and power the next AI die at scale.

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