FinFET scaling ran out of electrostatic headroom. Gate-all-around (GAA) nanosheet—or RibbonFET-class—devices wrap the channel so leakage and drive can be tuned for the dense logic AI SoCs and CPUs need. By mid-2026, leading foundry roadmaps had moved GAA from symposium charts into risk production on 18A-family nodes, often paired with backside power delivery.
That combination is the industrial point. GAA is the transistor chapter; backside power is the wiring chapter. Together they define who can sell leading-edge AI silicon when every watt and every square millimeter counts.
What GAA is meant to buy
- Better electrostatics — Tighter control at short gate lengths than FinFET.
- Design knobs — Nanosheet width and stack count trade drive current versus capacitance.
- A scaling runway — Foundation for later vertical device ideas such as CFET.
What still decides volume
Yield on nanosheet formation, epi, and contact. Design-technology co-optimization must land before customer tapeouts look cheap. IP reuse across 18A and 18A-P-class variants helps, but libraries, PDKs, and packaging still gate time-to-silicon. GAA does not erase HBM or advanced packaging bottlenecks—it only unlocks the logic die that those packages must carry.
What to watch next
- Risk-to-volume conversion rates and customer product announcements on GAA nodes.
- Measured power/performance deltas versus last FinFET nodes in real AI dies.
- How quickly second-source foundries close the GAA gap—or stay on extended FinFET.
High-NA prints the patterns; HBM feeds the die. GAA is the transistor chapter of the same AI silicon race.